/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_EMMC_HW_H
#define RK_EMMC_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the EMMC.
 */
#define RK_EMMC_SDMASA_OFFSET               0x0000U /* SDMA System Address Register */
#define RK_EMMC_BLOCKSIZE_OFFSET            0x0004U /* Block Size Register */
#define RK_EMMC_BLOCKCOUNT_OFFSET           0x0006U /* Block Count Register */
#define RK_EMMC_ARGUMENT_OFFSET             0x0008U /* Argument Register */
#define RK_EMMC_XFER_MODE_OFFSET            0x000CU /* Transfer Mode Register */
#define RK_EMMC_CMD_OFFSET                  0x000EU /* Command Register */
#define RK_EMMC_RESP01_OFFSET               0x0010U /* Response Register 0/1 */
#define RK_EMMC_RESP23_OFFSET               0x0014U /* Response Register 2/3 */
#define RK_EMMC_RESP45_OFFSET               0x0018U /* Response Register 4/5 */
#define RK_EMMC_RESP67_OFFSET               0x001CU /* Response Register 6/7 */
#define RK_EMMC_BUF_DATA_OFFSET             0x0020U /* Buffer Data Port Register */
#define RK_EMMC_PSTATE_OFFSET               0x0024U /* Present State Register */
#define RK_EMMC_HOST_CTRL1_OFFSET           0x0028U /* Host Control 1 Register */
#define RK_EMMC_PWR_CTRL_OFFSET             0x0029U /* Power Control Register */
#define RK_EMMC_BGAP_CTRL_OFFSET            0x002AU /* Block Gap Control Register */
#define RK_EMMC_CLK_CTRL_OFFSET             0x002CU /* Clock Control Register */
#define RK_EMMC_TOUT_CTRL_OFFSET            0x002EU /* Timeout Control Register */
#define RK_EMMC_SW_RST_OFFSET               0x002FU /* Software Reset Register */
#define RK_EMMC_NORMAL_INT_STAT_OFFSET      0x0030U /* Normal Interrupt Status Register */
#define RK_EMMC_ERROR_INT_STAT_OFFSET       0x0032U /* Error Interrupt Status Register */
#define RK_EMMC_NORMAL_INT_STAT_EN_OFFSET   0x0034U /* Normal Interrupt Status Enable Register */
#define RK_EMMC_ERROR_INT_STAT_EN_OFFSET    0x0036U /* Error Interrupt Status Enable Register */
#define RK_EMMC_NORMAL_INT_SIGNAL_EN_OFFSET 0x0038U /* Normal Interrupt Signal Enable Register */
#define RK_EMMC_ERROR_INT_SIGNAL_EN_OFFSET  0x003AU /* Error Interrupt Signal Enable Register */
#define RK_EMMC_AUTO_CMD_STAT_OFFSET        0x003CU /* Auto CMD Error Status Register */
#define RK_EMMC_HOST_CTRL2_OFFSET           0x003EU /* Host Control 2 Register */
#define RK_EMMC_CAPABILITIES1_OFFSET        0x0040U /* Capabilities Register 1 */
#define RK_EMMC_CAPABILITIES2_OFFSET        0x0044U /* Capabilities Register 2 */
#define RK_EMMC_FORCE_AUTO_CMD_STAT_OFFSET  0x0050U /* Force Event Register for Auto CMD Error Status Register */
#define RK_EMMC_FORCE_ERR_INT_STAT_OFFSET   0x0052U /* Force Event Register for Error Interrupt Status Register */
#define RK_EMMC_ADMA_ERR_STAT_OFFSET        0x0054U /* ADMA Error Status Register */
#define RK_EMMC_ADMA_SA_OFFSET              0x0058U /* ADMA System Address Register */
#define RK_EMMC_PRESET_INIT_OFFSET          0x0060U /* Preset Value for Initialization Register */
#define RK_EMMC_PRESET_DS_OFFSET            0x0062U /* Preset Value for Default Speed Register */
#define RK_EMMC_PRESET_HS_OFFSET            0x0064U /* Preset Value for High Speed Register */
#define RK_EMMC_PRESET_SDR12_OFFSET         0x0066U /* Preset Value for SDR12 Register */
#define RK_EMMC_PRESET_SDR25_OFFSET         0x0068U /* Preset Value for SDR25 Register */
#define RK_EMMC_PRESET_SDR50_OFFSET         0x006AU /* Preset Value for SDR50 Register */
#define RK_EMMC_PRESET_SDR104_OFFSET        0x006CU /* Preset Value for SDR104 Register */
#define RK_EMMC_PRESET_DDR50_OFFSET         0x006EU /* Preset Value for DDR50 Register */
#define RK_EMMC_ADMA_ID_OFFSET              0x0078U /* ADMA3 Integrated Descriptor Address Register */
#define RK_EMMC_SLOT_INTR_STATUS_OFFSET     0x00FCU /* Slot Interrupt Status Register */
#define RK_EMMC_HOST_CNTRL_VERS_OFFSET      0x00FEU /* Host Controller Version Register */
#define RK_EMMC_CQVER_OFFSET                0x0180U /* Command Queuing Version Register */
#define RK_EMMC_CQCAP_OFFSET                0x0184U /* Command Queuing Capabilities Register */
#define RK_EMMC_CQCFG_OFFSET                0x0188U /* Command Queuing Configuration Register */
#define RK_EMMC_CQCTRL_OFFSET               0x018CU /* Command Queuing Control Register */
#define RK_EMMC_CQIS_OFFSET                 0x0190U /* Command Queuing Interrupt Status Register */
#define RK_EMMC_CQISE_OFFSET                0x0194U /* Command Queuing Interrupt Status Enable Register */
#define RK_EMMC_CQISGE_OFFSET               0x0198U /* Command Queuing Interrupt Signal Enable Register */
#define RK_EMMC_CQIC_OFFSET                 0x019CU /* Command Queuing Interrupt Coalescing Register */
#define RK_EMMC_CQTDLBA_OFFSET              0x01A0U /* Command Queuing Task Descriptor List Base Address Register */
#define RK_EMMC_CQTDBR_OFFSET               0x01A8U /* Command Queuing Door Bell Register */
#define RK_EMMC_CQTCN_OFFSET                0x01ACU /* Command Queuing Task Clear Notification Register */
#define RK_EMMC_CQDQS_OFFSET                0x01B0U /* Command Queuing Device Queue Status Register */
#define RK_EMMC_CQDPT_OFFSET                0x01B4U /* Command Queuing Device Pending Tasks Register */
#define RK_EMMC_CQTCLR_OFFSET               0x01B8U /* Command Queuing Task Clear Register */
#define RK_EMMC_CQSSC1_OFFSET               0x01C0U /* Command Queuing Send Status Configuration 1 Register */
#define RK_EMMC_CQSSC2_OFFSET               0x01C4U /* Command Queuing Send Status Configuration 2 Register */
#define RK_EMMC_CQCRDCT_OFFSET              0x01C8U /* Command Queuing Command Response For Direct Command Register */
#define RK_EMMC_CQRMEM_OFFSET               0x01D0U /* Command Queuing Command Response Mode Error Mask Register */
#define RK_EMMC_CQTERRI_OFFSET              0x01D4U /* Command Queuing Task Error Information Register */
#define RK_EMMC_CQCRI_OFFSET                0x01D8U /* Command Queuing Command Response Index Register */
#define RK_EMMC_CQCRA_OFFSET                0x01DCU /* Command Queuing Command Response Argument Register */
#define RK_EMMC_VER_ID_OFFSET               0x0500U /* Host Version ID Register */
#define RK_EMMC_VER_TYPE_OFFSET             0x0504U /* Host Version Type Register */
#define RK_EMMC_HOST_CTRL3_OFFSET           0x0508U /* Host Control 3 Register */
#define RK_EMMC_EMMC_CTRL_OFFSET            0x052CU /* EMMC Control Register */
#define RK_EMMC_BOOT_CTRL_OFFSET            0x052EU /* Boot Control Register */
#define RK_EMMC_AT_CTRL_OFFSET              0x0540U /* Tuning Control Register */
#define RK_EMMC_AT_STAT_OFFSET              0x0544U /* Tuning Status Register */
#define RK_EMMC_DLL_CTRL_OFFSET             0x0800U /* DLL Global Control Register */
#define RK_EMMC_DLL_RXCLK_OFFSET            0x0804U /* DLL Control Register For Receive Clock */
#define RK_EMMC_DLL_TXCLK_OFFSET            0x0808U /* DLL Control Register For Transmit Clock */
#define RK_EMMC_DLL_STRBIN_OFFSET           0x080CU /* DLL Control Register For Strobe Input */
#define RK_EMMC_DLL_CMDOUT_OFFSET           0x0810U /* DLL Control Register For Command Output */
#define RK_EMMC_DLL_STATUS0_OFFSET          0x0840U /* DLL Status Register 0 */
#define RK_EMMC_DLL_STATUS1_OFFSET          0x0844U /* DLL Status Register 1 */

#ifdef __cplusplus
}
#endif

#endif /* RK_EMMC_HW_H */